Multiprocessor computer backlane bus

Details Multiprocessor computer backlane bus Multiprocessor computer backlane bus

1997-03-25

1998-07-28

Chung, Phung M.

Excavating

371 201, 371 671, G06F 1540, H04L 100

Patent

active

057870950

ABSTRACT:
A computer bus includes a first original signal line, a second redundant signal line, circuitry connected to the first original signal line and the second redundant signal line for driving the first original signal line and the second redundant signal line so as to convey on each identical information, circuitry for receiving signals on the first original signal line and the second redundant signal line, and error checking circuitry for comparing the signals on the first original signal line and the second redundant signal line and for indicating an error if the signals differ. By providing redundant signals for each signal that cannot be check with parity (for example wired-OR signals), the potential for single undetected points of failure is eliminated. In accordance with another embodiment of the invention, a computer having multiple modules connected by a backplane bus.

REFERENCES:
patent: 4817094 (1989-03-01), Lebizay et al.
patent: 5200963 (1993-04-01), Chau et al.
patent: 5249188 (1993-09-01), McDonald
patent: 5345566 (1994-09-01), Tanji et al.
patent: 5428768 (1995-06-01), Sugahara
patent: 5483639 (1996-01-01), Haeussler et al.

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