Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1997-12-17
2000-06-13
Follansbee, John A.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
G06F 1580
Patent
active
060761520
ABSTRACT:
A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors ("MAP") in the memory subsystem. The MAP may comprise one or more field programmable gate arrays ("FPGAs") which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory ("ROM") located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time. A computer system memory structure MAP disclosed herein may function in normal or direct memory access ("DMA") modes of operation and, in the latter mode, one device may feed results directly to another thereby allowing pipelining or parallelizing execution of a user defined algorithm. The system of the present invention also provides a user programmable performance monitoring capability and utilizes parallelizer software to automatically detect parallel regions of user applications containing algorithms that can be executed in the programmable hardware.
REFERENCES:
patent: 5230057 (1993-07-01), Shido et al.
patent: 5892962 (1999-04-01), Cloutier
Yun et al., A Distributed Memory MIMD Multi-Computer with Reconfigurable Custom Computing Capabilities IEEE, Dec. 13, 1997, pp. 8/13 especially pp. 9-11.
Gokhale, M., et al., "Processing in Memory: The Terasys Massively Parellel PIM Array".COPYRGT.Apr. 1995, IEEE, pp. 23-31.
DeHon, A., et al., "MATRIX A Reconfigurable Computing Device with Configurable Instruction Distribution", Hot Chips IX, Aug. 25-26, 1997, Stanford, California, MIT Artifical Intelligence Laboratory.
Buell, D., et al., "Splash 2: FPGAs in a Custom Computing Machine-Chapter 1-Custom Computing Machines: An Introduction", pp. 1-11, http://ww.computer.org/espress/catalog/bp07413/spls-ch1.html(originally believed published in J.of Supercomputing, voil. IX, 1995, pp. 219-230.
Agarwal, A, et al., "The Raw Compiler Project", pp. 1-12, http://cag-www.Ics.mit.edu/raw, Proceedings of the Second SUIF Compiler Workshop, Aug. 21-23,1997.
Hartenstein, R.W. et al. "A General Approach in System Design Intergrated Reconfigurable Accelerators", http://xputers.informatik.uni-kl.de/papers026-1.html, IEEE 1996 Conference, Austin, TX, Oct. 9-11, 1996.
Huppenthal Jon M.
Leskar Paul A.
Follansbee John A.
Kubida, Esq. William J.
SRC Computers, Inc.
LandOfFree
Multiprocessor computer architecture incorporating a plurality o does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiprocessor computer architecture incorporating a plurality o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiprocessor computer architecture incorporating a plurality o will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2079042