Multiprocessor circuit

Details Multiprocessor circuit Multiprocessor circuit

1993-12-14

1995-06-06

Harvey, Jack B.

Boots, shoes, and leggings

364DIG1, 364229, 3642292, 3642302, 3642303, G06F 1326

Patent

active

054230497

ABSTRACT:
This multiprocessor circuit has interruption restriction circuits connected between the interruption line, which is provided for inputting interruption signals, and each of the CPUs connected in parallel. The interruption restriction circuits restrict the input of interruption signals to each CPU under certain conditions. Each interruption restriction circuit counts the number of interruption signals received by each corresponding CPU during a specified period set at the timer, using a counter. When the count for a CPU exceeds the predetermined value, the multiprocessor circuit causes the input disabling means to disable the input of interruption signals to that CPU for a certain period of time and thereby distributes the interruption signals to a plurality of CPUs more equally.

REFERENCES:
patent: 3665404 (1970-04-01), Werner
patent: 4099255 (1978-07-01), Stanley et al.
patent: 4816990 (1989-05-01), Williams
patent: 4930070 (1990-05-01), Yonekura et al.
patent: 4935894 (1990-06-01), Ternes et al.
patent: 5031089 (1991-07-01), Liu et al.
patent: 5099414 (1992-03-01), Cole et al.
patent: 5125093 (1992-06-01), McFarland
patent: 5179707 (1993-01-01), Piepho

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