Multiprocessor cache examiner and coherency checker

Details Multiprocessor cache examiner and coherency checker Multiprocessor cache examiner and coherency checker

1993-06-30

1995-04-11

Voeltz, Emanuel T.

Boots, shoes, and leggings

364578, 364400, 395375, 395400, 395425, G05B 1902, G06F 1300

Patent

active

054065046

ABSTRACT:
An arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangement includes a plurality of processes configured to acquire information from selected block entries of the caches. The information is then compared with an array of predetermined valid cache states contained in a state table to detect invalid cache states. A cache examining protocol defines the operational procedures followed by the processes when acquiring and examining the information.

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