Multiprocessor bus protocol

Details Multiprocessor bus protocol Multiprocessor bus protocol

1986-03-28

1989-12-19

Eng, David Y.

Boots, shoes, and leggings

364241, 3642411, 3642283, 3642715, 3642292, 3642408, 3642409, 3642401, G06F 1300, G06F 1312, G06F 1314, G06F 1322

Patent

active

048886840

ABSTRACT:
A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.

REFERENCES:
patent: 3668649 (1972-06-01), Pedersen et al.
patent: 4369864 (1987-01-01), Katzman
patent: 4447871 (1984-05-01), Terada
patent: 4471425 (1984-09-01), Yamaguchi et al.
patent: 4481572 (1984-11-01), Ochsner
patent: 4636939 (1987-01-01), Fildes

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