Multiprocessor bus debugger

Excavating

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Details

371 151, 395575, G06F 1100

Patent

active

052048640

ABSTRACT:
An arbiter circuit has a first flip flop and a second flip flop. The first flip flop sends a bus request (BR*) signal to the VME bus by toggling the bus request signal when a trigger signal is received. The second flip flop sends a bus busy (BBSY*) signal to the VME bus by toggling the bus busy signal when a bus grant (BG*) signal is received from the VME bus. The second flip flop releases the bus busy (BBSY*) signal on the VME bus when a reset is commanded at the end of the test by a controller or a push button switch. Tests are performed by writing to the bus and reading from the bus by an address register, a write data register and a read data register connected to the address and data lines of the VME bus. The trigger signal source is selected by a trigger select circuit. A data transfer acknowledge trigger can be selected to trigger every time the data transfer acknowledged (DTACK*) line from the VME bus indicates a data transfer on the bus. An external trigger can be selected where a particular trigger source, such as that selected by a moveable test probe, can be used as a trigger. An address trigger can be selected to trigger when the VME bus address matches a particular address. A trigger address can be selected to trigger when the VME bus address matches a particular address a specified number of times.

REFERENCES:
patent: 4281380 (1981-07-01), DeMesa
patent: 4467418 (1984-08-01), Quinquis
patent: 4951283 (1990-08-01), Mastrocola
patent: 4958347 (1990-09-01), White
B. Sacks, "VME Bus Anomaly Trigger", Ultra View Corp., Oct. 1985, pp. 1-4.
VMEbus Specification, Rev. C.1, Motorola, Printex Publishing, Inc. Oct. 1985, Selected pages and portions.
Horowitz, Paul, and Hill, Winfield, The Art of Electronics, 2nd Edition, 1989, pp. 710, 711, 821 and 823-825.

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