Multiprocessor array error detection and recovery apparatus

Details Multiprocessor array error detection and recovery apparatus Multiprocessor array error detection and recovery apparatus

1984-08-27

1986-12-02

Fleming, Michael R.

Excavating

371 16, G06F 1100

Patent

active

046270540

ABSTRACT:
A multiprocessor array is described in which a central controlling microprocessor interfaces over commonly connected address and data busses to a plurality of peripheral microprocessors. A memory mapped I/O interface controls access to and from the busses for mutual receipt and exchange of signals between the processors and mutual exchange and receipt of data among the processors. The individual processors are selectively isolatable by a plurality of three state switch means connected between each processor and the interconnecting data and address busses. Error detection and control logic is connected via control lines to the individual processors and responsive to an error indication thereof, activates a multipoint error signal to all said microprocessors over a control line, which signal is interpreted by the processor then controlling said busses as a signal to deactivate its operation and as a signal at said control microprocessor to invoke an interrupt for analyzing the causes of said error. The control microprocessor can issue memory mapped I/O instructions to the individual three state selective isolation means and/or to any of the I/O microprocessors to respectively isolate the processors from said busses or to control said processors in an error analysis routine. The apparatus further includes a machine check register and a bus master register associated with said control microprocessor which registers can be written in by said control microprocessor and read from only by one of said I/O microprocessors.

REFERENCES:
patent: 4347563 (1982-08-01), Paresdes
patent: 4371952 (1983-02-01), Schuck
patent: 4392199 (1983-07-01), Schmitter
patent: 4395755 (1983-07-01), Wakai
patent: 4453213 (1984-06-01), Romagosa

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