Multiprocessor array

Details Multiprocessor array Multiprocessor array

2006-08-22

2006-08-22

Rodriguez, Paul L. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Computer or peripheral device

C710S240000, C710S241000

Reexamination Certificate

active

07096177

ABSTRACT:
A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

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Schwartz, Mischa; “Telecommunications Networks: Protocols, Modeling and Analysis”, 1987, Addison-Wesley.

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