Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Patent
1996-07-01
1999-09-28
Dinh, Dung C.
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
711141, 711144, 711145, G06F 1342
Patent
active
059580194
ABSTRACT:
When a processor within a computer system performs a synchronization operation, the system interface within the node delays subsequent transactions from the processor until outstanding coherency activity is completed. Therefore, the computer system may employ asynchronous operations. The synchronization operations may be used when needed to guarantee global completion of one or more prior asynchronous operations. In one embodiment, the synchronization operation is placed into a queue within the system interface. When the synchronization operation reaches the head of the queue, it may be initiated within the system interface. The system interface further includes a request agent comprising multiple control units, each of which may concurrently service coherency activity with respect to a different transaction. Furthermore, the system interface includes a synchronization control vector register which stores a bit for each control unit. Upon initiation of the synchronization operation within the system interface, bits corresponding to those control units which are performing coherency activity (i.e. those which are not idle) are set while other bits are cleared. As each control unit returns to the idle state, the corresponding bit is cleared as well. Once all the bits within the synchronization control vector register are cleared, the coherency activity which was outstanding when the synchronization operation was initiated is complete. The synchronization operation may then be completed.
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Guzovskiy Aleksandr
Hagersten Erik E.
Nesheim William A.
Nguyen Hien
Wong-Chan Monica C.
Dinh Dung C.
Kivlin B. Noel
Sun Microsystems Inc.
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