Multiprocessing interrupt arrangement

Details Multiprocessing interrupt arrangement Multiprocessing interrupt arrangement

1981-12-02

1986-08-05

Shaw, Gareth D.

G06F 900

Patent

active

046045007

ABSTRACT:
There is disclosed an interrupt arrangement for use in a multiprocessing system where it is desired to specifically direct interrupts from one processor to any other processor. The arrangement treats the interrupt signal as a data communication between processors. In this regard, common address space is set aside, on a system basis, for interrupt signals. A sending processor first contends for the system bus and then addresses a message to a specific target processor. The message is received at the target processor over the regular communication channel and stored in a FIFO memory. Interrupt messages filter through the memory in order of arrival and cause interrupts to occur at the target processor. The information at the output of the FIFO memory controls the processing of the interrupt.

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patent: 4320451 (1982-03-01), Bachman et al.
patent: 4323967 (1982-04-01), Peters et al.
patent: 4414624 (1983-11-01), Summer et al.
patent: 4420806 (1983-12-01), Johnson et al.
patent: 4424561 (1984-01-01), Stanley

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