Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
2002-08-19
2004-12-21
Bui, Bryan (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
C702S035000, C702S182000, C438S010000, C438S014000, C324S750010, C324S757020
Reexamination Certificate
active
06834246
ABSTRACT:
FIELD OF INVENTION
This invention relates to testing semiconductor wafers and more particularly to determining the cost savings of a multiprobe sample (blob) test in lieu of 100% probe test.
BACKGROUND OF INVENTION
Massive quantities of completed fabricated integrated circuits are functionally tested by being probed in wafer form by multiprobe test device before separation and encapsulation of the integrated circuits into individual packages (assembly). Since the circuits are again tested after assembly and before shipment to customers, the justification for probing wafers is to avoid the cost of assembly on non-functional circuits. Wafer testing adds a significant cost to the wafers and when chip yields are very high, the cost of wafer test is more than the resultant cost that would result from assembly of small number of non-functional circuits. A sample test procedure is therefore employed to identify wafers with high enough yield to allow cost effective avoidance of 100% test. The yield point below which this procedure is not cost effective is calculated as a hurdle. If the sample yield on a wafer is below the point where reduced test is cost effective, that wafer is 100% tested. Since this yield threshold is high, a significant number of wafers must be fully tested adding extra cost, decreasing test capacity and hampering production planning by introducing variability in manufacturing cycle time.
Sample wafer testing has been done with a procedure called Good Sample Probe (GSP). The procedure is illustrated in FIG.
1
and is as follows.
Divide the wafer into cells containing a number of chips, e.g. a 4×3 chip cell would contain 12 chips.
FIG. 2
illustrates a wafer sample plan. The chips are bounded by black lines and the cells are bounded by very light grey lines surrounding the twelve chips. One of the good cells is circled and presented as expanded view with the cell outlined in black.
Randomly select one chip within each cell. The one chip for each cell is outlined in white in bad areas or totally white in good areas in FIG.
2
. The set of selected chips is the sample to be tested.
Test the set of sample chips and calculate the yield of the sample. In
FIG. 2
white represents good chips.
Calculate the yield threshold point Y
TH′
below which the savings afforded by reduced testing is greater than the cost of assembling some quantity of failing chips.
If the sample yield is below the threshold, the remaining chips on the wafer must be 100% tested to avoid the high cost of assembly on chips that will fail final test.
FIG. 3
illustrates wafer map of fully probed wafer where the wafer yield is 80.63%.
If the sample yield is above the threshold, the wafer can be shipped for assembly without further testing. One additional test operation is, however, performed on this wafer.
FIG. 2
shows the wafer sample plan where the sample yield was 80.91%. The yield threshold is 97.15%, so the cost of assembly of bad chips would exceed the savings of reduced sample test. The white chips are good chips, the band of light grey chips around the perimeter is the excluded chips (not tested or assembled). All other grey shades are test failures.
Perform “blob test” on wafers that passed the sample yield threshold criterion.
The Blob test is a procedure that tests all chips adjacent to any sample chip that failed during the initial pass. All neighbors of any additional failures are then tested. This cycle is repeated until no new test failures are found. All bad chips in close proximity to each other will be tested and marked as bad. Since failing chips often occur in tight groups, blob test finds and marks as bad a significant fraction of additional, as yet untested chips that may exist on the wafer, reducing assembly cost with only a minimal increase in test cost.
It is desirable to predict the effect of blob test in GSP sample testing and improve the decision to perform the blob test in lieu of 100% probe testing.
SUMMARY OF INVENTION
In accordance with one embodiment of the present invention a method is provided to identify such blobs and determine when it is cost effective to do blob test in lieu of 100% probe test.
In accordance with an embodiment of the present invention on wafers with low sample yield, implement a special regional analysis to identify potential concentrations of bad chips. Many wafers can then use a process called “blob test” in place of 100% probe test, and still avoid assembly and subsequent scrap of large quantities of bad chips.
In accordance with an embodiment of the present invention a method for identifying when a blob test would be sufficient to reduce the number of untested bad chips to a level where cost savings can still be realized includes the steps of analyzing the sample results to identify blobs that will be tested out by blob test, estimating the yield of the remaining area of the wafer and determining if that residual yield is high enough to avoid 100% probe test and still realize a cost savings.
In accordance with an embodiment of the present invention a method of predicting the effect of blob test in GSP sample testing includes the steps of extracting failure density maps from sample test results, where the density of any failed cell is expressed as the number of adjacent failing sample cells; determining the existence of local concentration of bad chips (blobs) as the occurrence of a detection density value above a threshold which can be adjusted to control the sensitivity of blob detection; determining the extent of such identified blobs as the occurrence of adjacent cells with density values above an inclusion threshold, which can also be adjusted to control the sensitivity of blob extent determination; calculating a residual sample yield Y
NB
for the areas outside blob regions using the total sample cell count N
S
, the passing cell count N
G
, and the count of cells in blobs N
B
by equation:
Y
NB
=
N
G
N
S
-
N
B
;
and re-evaluating the decision of whether 100% probe test is required or if the cost savings can still be realized by performing only blob test.
REFERENCES:
patent: 5326709 (1994-07-01), Moon et al.
patent: 6021380 (2000-02-01), Fredriksen et al.
patent: 6043101 (2000-03-01), Stubblefield et al.
Gharis Eugene T.
Reeves George W.
Stubblefield Todd D.
Brady III W. James
Bui Bryan
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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