Multiport RAM and information processing unit

Static information storage and retrieval – Magnetic bubbles – Guide structure

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36523005, 36518904, 365203, G06F 1300, G11C 700, G11C 11413

Patent

active

052768376

ABSTRACT:
A multiport RAM comprises a memory section formed of many unit memory cells which are positioned to an orderly matrix of M columns by N rows, a write address designation section for designating the unit memory cells on the prescribed rows, a write clock signal by which the input data is synchronized in the write operation that the data is written in the unit memory cells designated by the write address designation section, a read address designation section for designating the unit memory cells on one or more prescribed rows, and a read clock signal by which the output data is synchronized in the read operation that the data is read out from the unit memory cells designated by the read address designation section, having no relation with the write private clock signal.

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patent: 5062081 (1991-10-01), Runaldue
K. Sakaue et al., "A 0.8.mu.BiCMOS ATM switch on the 800 Mbps asynchronous buffered banyan network", 1990 Symposium on VLSI Circuits, Digest of Technical Papers, Jun. 7-9, 1990, pp. 65-66.

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