Multiport memory with improved timing of word line selection

Details Multiport memory with improved timing of word line selection Multiport memory with improved timing of word line selection

1990-07-16

1991-04-09

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

36523005, 36523009, G11C 800

Patent

active

050070282

ABSTRACT:
This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.

REFERENCES:
patent: 4633411 (1986-12-01), Ishimoto
patent: 4720819 (1988-01-01), Pinkham et al.

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