Boots – shoes – and leggings
Patent
1996-03-26
1998-04-07
Swann, Tod R.
Boots, shoes, and leggings
364DIG1, 364DIG2, 3642384, 3642448, 395477, 395478, 395481, 395494, 395495, G06F 1200, G06F 1314
Patent
active
057375690
ABSTRACT:
An arbitration circuit and method for a multiport high speed memory in a computer microprocessor. A plurality of addresses are provided to a plurality of ports. The addresses are decoded in a plurality of decoders. The decoded output lines are compared in a comparison circuitry to determine if one or more of the ports is requesting access to the same memory line, and a comparison bit indicative of a match is outputted. If asserted, the comparison bit disables a line driver so that only one of the wordlines in a particular memory line is driven at any one time.
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Chu Ching-Hua
Nadir James
Intel Corporation
Swann Tod R.
Thai Tuan V.
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