Multiplying unit circuit

Details Multiplying unit circuit Multiplying unit circuit

1990-09-07

1991-04-23

Malzahn, David H.

Boots, shoes, and leggings

364707, G06F 752

Patent

active

050105108

ABSTRACT:
A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and furnishes the sum to the next stage. A control circuit is provided that disables the outputs of each stage of the array until the operation in the particular stage is completed. The disabling of outputs reduces power consumption.

REFERENCES:
patent: 4302819 (1981-11-01), Ware
patent: 4409665 (1983-10-01), Tubbs
patent: 4736335 (1988-04-01), Barkan
patent: 4748583 (1988-05-01), Noll

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