Multiply pipe round adder

Boots – shoes – and leggings

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Details

364745, 364748, G06F 752, G06F 738

Patent

active

057269270

ABSTRACT:
A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

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patent: 5434809 (1995-07-01), Taniguchi
patent: 5444647 (1995-08-01), Komoda
patent: 5500812 (1996-03-01), Saishi et al.
patent: 5506800 (1996-04-01), Dao-Trong
patent: 5521855 (1996-05-01), Yamazaki

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