Multiply and divide unit for a high speed processor

Details Multiply and divide unit for a high speed processor Multiply and divide unit for a high speed processor

1984-04-11

1987-05-12

Malzahn, David H.

Boots, shoes, and leggings

364767, G06F 752

Patent

active

046655000

ABSTRACT:
A High Speed Multiplier/Divider for use with high speed processors that have dedicated adders, registers, controls and logic for performing a multiply operation, a multiply and add operation, and a divide operation. The multiply/divide circuit has capability of multiplying a 16 bit word times a 16 bit word that produces a 32 bit product with divide being the inversed of the multiplication operation and may use signed or unsigned multiply/divide. A Booth algorithm is used to implement the multiply operation and the multiply/divide operations are operating asynchronous, that is, at the completion of one set of operations, the next set is implemented.

REFERENCES:
patent: 3293420 (1966-12-01), Pitkowsky et al.
patent: 3761698 (1973-09-01), Stephenson
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4238833 (1980-12-01), Ghest et al.
patent: 4337519 (1982-06-01), Nishimoto

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