Multiply and accumulate unit (MAC) and method therefor

Details Multiply and accumulate unit (MAC) and method therefor Multiply and accumulate unit (MAC) and method therefor

2000-01-18

2003-06-17

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06581086

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multiply and accumulate units, and specifically to accuracy and precision balancing of results from a multiply and accumulate unit.
BACKGROUND OF THE INVENTION
As data processing systems are required to process increasing amounts of information and perform a variety of operations on data, coprocessors are often added to perform specific functions. In video and audio applications the data is compressed and/or decompressed to improve the throughput of the transmission system. These systems require arithmetic and logical operation capability as well as more complex operations to accommodate compression, modulation, demodulation, etc. Typically, these functions are performed using software or some dedicated hardware.
Many of the more complicated operations result in data rate distortion. For example, when input data is compressed, the amount of output data that will result from a given input data stream is often not determinable. Data rate distortion adds to the flexiblity of the data processing system and is a requirement of most systems that process video, audio and communication information.
Software routines provide a flexible, convenient method of processing information, but also introduce latency into the systems, as typically many cycles are required to perform each of the various algorithms. Hardware solutions are less flexible, but provide a faster computation. Hardware and coprocessors typically have an input/output (I/O) bus for communication with the main processor, such as a central processing unit (CPU), and the rest of the data processing system. The I/O bus prevents the coprocessor from simultaneously receiving data while outputting data to the data processing system. This prevents these coprocessors from pipelining instructions where instructions are received while others are processed.
With respect to execution units that perform multiply and accumulate functions, such as a multiply and accumulate unit (MAC), a series of operands are multiplied and the product of each multiplication is added to previous results. In a fixed-point operation using fractional representations, the operands are fractions and therefore the product of a multiplication is always less than one (1), and are therefore always to the right of the radix point. In contrast, the sum of an addition may exceed one (1) and may in fact become quite large. The sum of the addition may be scaled to balance bit-length with precision, i.e. more bits increase the precision but require more storage and calculation capability. If a predetermined number of bits are allowed for further processing, where the predetermined number of bits is less than the total number of bits in the addition sum, each significant bit to the left of the radix point reduces the number of bits allowed to the right of the radix point. In this case, the scaling maintains accuracy while sacrificing precision.
Typically, scaling involves determining a predetermined range of values within which the sum of each addition is to fall. The number of bits allowed to the right and left of the radix point is determined by the user in advance to actual processing according to the predetermined range of values. When the sum of an addition is outside the predetermined range of values, the predetermined range of values must be adjusted. Often the predetermined range is an estimate of where the results should fall, and actual data may not follow the estimate. In such a case the range is adjusted and calculations from this point on use the new range. A problem exists in the current calculation, as the result of a MAC operation is the final result of multiple accumulations, i.e. iterations of the MAC unit, and the accumulations before the error where scaled by a first factor while those after the error are scaled by a second factor. The prior art solution is to perform the entire MAC operation a second time using the second, or adjusted, range. This increases the operation time of the MAC unit, and may cause delays in pipelined operations.
Therefore, there is a need for a method of scaling results from a MAC unit that reduces the time required to correct the result and adjust the scaling factor. Additionally, a need exists for a method of identifying overflows in the MAC unit calculations to prevent further errors from propagating through the data processing system without requiring recalculation of operations already performed.


REFERENCES:
patent: 5623683 (1997-04-01), Pandya
patent: 5644519 (1997-07-01), Yatim et al.
patent: 6233596 (2001-05-01), Kubota et al.
patent: 6314443 (2001-11-01), Seal

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