Multiply and accumulate circuit

Details Multiply and accumulate circuit Multiply and accumulate circuit

1997-09-04

1998-12-08

Malzahn, David H.

Boots, shoes, and leggings

36473602, 36476005, G06F 752

Patent

active

058479813

ABSTRACT:
A multiply accumulate circuit (600) includes a multiply accumulate reduction circuit (527) that generates P current accumulated operands during an iteration. P operand registers (582) are coupled to the multiply accumulate reduction circuit (527). A corresponding one of the P current accumulated operands is stored in each of the P operand registers (582) in place of one of the P partial accumulated operands in response to the iteration. Each of P feedback paths (593) couples one of P outputs of the P operand registers (582) to a corresponding one of P feedback inputs of the multiply accumulate reduction circuit (527). An adder (561) that is coupled to the P outputs through isolation circuits (570) generates an output (551) in N iterations that is a sum of N products, each being a product of one of a series of N multipliers and one of a series of N multiplicands.

REFERENCES:
patent: 4727507 (1988-02-01), Miyanaga
patent: 5175702 (1992-12-01), Beraud et al.
patent: 5220525 (1993-06-01), Anderson et al.
patent: 5602766 (1997-02-01), Bauer et al.
patent: 5659495 (1997-08-01), Briggs et al.
M. R. Shapiro "Design and Clocking of VLSI Multipliers", Technical Report No. CSL-TR-89-397, pp. 1-52, Computer Systems Laboratory, Stanford University, Oct. 1989.
C.S. Wallace, "A Suggestion for Fast Multipliers", IEEE Transactions on Electronic Computers, vol. EC-13, pp. 14-17, Feb. 1964.

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