Multiply-adder unit

Details Multiply-adder unit Multiply-adder unit

1996-05-01

1998-07-21

Elmore, Reba I.

Boots, shoes, and leggings

G06F 738

Patent

active

057843058

ABSTRACT:
The invention provides a multiply-adder unit which has a reduced number of inputs to an adder tree to allow reduction of the amount of hardware and high speed operation. A bit width extender performs, upon unsigned operation, zero extension of one bit but performs, upon signed operation, sign extension of one bit for a multiplicand. A zero extender performs zero extension of 2 bits for a multiplier. A Booth's decoder cuts out an output of the zero extender in units of 3 bits successively shifting its cut-out start position by 2 bits toward the lower bits beginning with the uppermost bit and generates first to (k-1)th partial products and a kth partial product based on the cut out values and the output of the bit width extender. A selector selects, upon unsigned operation, the kth partial product but selects, upon signed operation, the output of the sign extender (addend after sign extension). A k-input adder tree adds the first to (k-1)th products and the output of the selector.

REFERENCES:
patent: 4852037 (1989-07-01), Aoki
patent: 5343416 (1994-08-01), Eisig et al.
patent: 5583804 (1996-12-01), Seal et al.
patent: 5659495 (1997-08-01), Briggs et al.
Neil H.E. Weste et al., Principles of CMOS VLSI Design: A Systems Perspective, AT&T, pp. 547-555 (1983).
C.S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Transactions on Electronic Computers EC-13(1): 14-17 (1964).

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