Multiply accumulator for two N bit multipliers and an M bit...

Details Multiply accumulator for two N bit multipliers and an M bit... Multiply accumulator for two N bit multipliers and an M bit...

2006-05-09

2006-05-09

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S603000, C708S628000

Reexamination Certificate

active

07043517

ABSTRACT:
A multiply accumulator performs a multiplication-and-addition operation for a first multiplier with N bits, a second multiplier with N bits, and an addend with M bits, wherein M is larger than 2N. The multiply accumulator includes a modified Booth encoder and a multiplication-and-addition unit. The modified Booth encoder performs a Booth encoding to either the first multiplier or its bit inversion by supplementing a multiplier sign bit behind a least significant bit of either the first multiplier or its bit inversion. The multiplication-and-addition unit includes a carry save adder tree and a sign extension adder and achieves a high speed of the multiplication-and-addition operation by simultaneously performing the multiplication and addition.

REFERENCES:
patent: 4740906 (1988-04-01), Renner et al.
patent: 5623683 (1997-04-01), Pandya
patent: 5847981 (1998-12-01), Kelley et al.
patent: 6542915 (2003-04-01), Dibrino et al.
patent: 6611856 (2003-08-01), Liao et al.

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