Multiply accumulate unit for processing a signal and method of o

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G06F 700

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active

059301600

ABSTRACT:
A multiply accumulate unit processes a signal according to a sum-of-products function based upon a plurality of multibit sampled values and a corresponding plurality of multibit constants. A multiply-add block receives the sampled values and the constants. A portion of each constant is selected. A plurality of multipliers multiple sampled values and selected portions of the corresponding constants. The products are added and shifted corresponding to the significance of the selected portion of the constants. These are added to generate a sum of sequential outputs of the multiply-add block. The multiply accumulate unit repeats operation employing the same sample values but portions of said corresponding constants having sequentially less significant bits. This sequence repeats until the sum of all prior sum-of-products functions has a desired level of accuracy.

REFERENCES:
patent: 4156876 (1979-05-01), Debuisser
Chevillat et al, "Pipelined hardware multiplier with extended precision", IBM Tech. Discl. Bull. vol. 23 No. 9, Feb. 1981 pp. 4322-4323.

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