Multiply-accumulate unit and method of operation

Details Multiply-accumulate unit and method of operation Multiply-accumulate unit and method of operation

2006-04-07

2010-06-01

Malzahn, David H (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07730118

ABSTRACT:
An arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, including a multiplier, addition circuitry, a result register, and accumulator circuitry. The multiplier arranged to receive first and second operands and operable to generate multiplication terms. The addition circuitry for receiving multiplication terms from the multiplier and operable to combine them to generate a multiplication result. The result register for receiving the multiplication result from the adder. The accumulator circuitry connected to receive a value stored in the result register and an accumulate control signal which determines whether the arithmetic unit implements a multiply or a multiply-accumulate instruction.

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Liao, Y, et al.: “A High-Performance and Low-Power 32-Bit Multiply-Accumulate Unit with Single-Instruction-Multiple-Data (SIMD) Feature”, IEEE Journal of Solid-State Circuits, IEEE Inc., New York, US, vol. 37, No. 7, Jul. 2002, pp. 926-931, XP001221317.

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