Multiplier using MOS channel widths for code weighting

Details Multiplier using MOS channel widths for code weighting Multiplier using MOS channel widths for code weighting

2006-03-28

2006-03-28

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical analog calculating computer

Particular function performed

C327S356000

Reexamination Certificate

active

07020675

ABSTRACT:
A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.

REFERENCES:
patent: 4801827 (1989-01-01), Metz
patent: 5438296 (1995-08-01), Kimura
patent: 5990737 (1999-11-01), Czarnul et al.
patent: 6456142 (2002-09-01), Gilbert

Affiliated with

Also associated with

Rating

Multiplier using MOS channel widths for code weighting does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiplier using MOS channel widths for code weighting, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplier using MOS channel widths for code weighting will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3609980