Multiplier in a galois field

Details Multiplier in a galois field Multiplier in a galois field

1987-10-09

1990-04-17

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

049186388

ABSTRACT:
A circuit effects regular multiplicaton of two field elements in a Galois field GF (2.sup.m). Each of the field elements is expressed by an m-bit binary number. The two field elements are applied to a binary multiplier array which generates (2m-1)-bit partial products. The partial products are divided by a generator polynomial of the Galois field to produce final m-bit binary products.

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patent: 4697248 (1987-09-01), Shirota
patent: 4745568 (1988-05-01), Onyszchuk et al.
Laws, Jr. et al., "A Cellular--Array Multiplier For GF(2.sup.m)", IEEE Trans. on Computers, Dec. 1971, pp. 1573-1578.
Wang et al., "YLSI Architectures for Computing Multiplications and Inverses in GF(2.sup.m)", IEEE Trans. on Computers, vol. c--34, No. 8, Aug. 1985, pp. 709-717.

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