Boots – shoes – and leggings
Patent
1991-01-18
1992-10-06
Nguyen, Long T.
Boots, shoes, and leggings
G06F 752
Patent
active
051538490
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The multiplication of x-place multiplicands (x=0, 1, 2. . .m-1) by a y-place multiplier factor (y=0, 1, 2. . .n-1) (m and n are whole, positive numbers) that are represented as binary numbers can be implemented according to FIG. 1. This shows a matrix MA that contains the partial products PP that arise in the multiplication. The multiplicand is thereby referenced A and the multiplier factor is referenced B. The partial products can be generated from the multiplier factor place and the multiplicand place with AND circuits. A product place P is generated by summing up the partial products per column of the matrix. A carry from the next, less significant place of the product is thereby also to be taken into consideration. Three fields can be distinguished in FIG. 1. Field III recites the partial products that are necessary for the multiplication. Field I recites partial products that are not necessary in the multiplication; the same is also true of Field II. The places of the matrix are recited with 0 in these Fields I and II.
AND circuits that form the partial products and adder circuits that sum up the partial products per column are thus required in order to construct a multiplier that multiplies according to the matrix of FIG. 1. When such a multiplier is to be realized, it is necessary that the AND circuits and the adder circuits are arranged in an especially advantageous way in order to create a realization on one chip with optimally low space requirement and optimally favorable transit time conditions. It is also necessary that such a multiplier can be very easily tested.
SUMMARY OF THE INVENTION
The object underlying the invention is comprised in specifying a multiplier that is constructed such that it satisfies the above-recited demands. In addition, the structure should be such that a multiplier having variable multiplicand word width and multiplier factor word width can be easily manufactured.
For achieving this object, the multiplier for operating a m-place multiplicand and an n-place multiplier factor both of which are represented as binary numbers comprises
a) m+n cells arranged side-by-side, respectively one per product place, whereof each cell respectively contains AND circuits for forming the partial products allocated to the product place and adder circuits for summing up the partial products for this product place,
b) the following relationship of the AND circuits and adder circuits within a cell: operates one bit of the multiplicand and one bit of the multiplier factor to form a partial product, products generated by an AND circuit to form a partial sum and a partial carry, partial sums of the first stage of the same product place and at least two partial carries of the first stage of the next-less significant product place to form a further partial sum and a further partial carry, sums of the second stage of the same product place and at least two partial carries of the second stage of the next-less significant product place to form a further partial sum and a further partial carry, circuits utilized tree-like in the individual stages until the plurality of partial sums and of partial carries from the next-less significant product place generated in a stage of the same product place is such that it can be operated with a final adder circuit to form a final sum bit and a final carry bit, preceding product place are operated in an adder circuit to form a value P of the corresponding product place, and
c) the following arrangement of the AND circuits and adder circuits within a cell: to which an adder circuit of the first stage for the output signals of this AND circuit adjoins, second stage for the preceding adder circuits of the first stage, appeared, the last adder circuit of the second stage is then followed by an adder circuit of the third stage that operates the output signals of the adder circuits of the second stage, final adder circuit has appeared.
It is especially beneficial for the realization on a semiconductor module and for the testability of th
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Becker Bernd
Mitchell Rebecca
Nerz Ulrich
Roth Wolfram
Soukup Holger
Nguyen Long T.
Siemens Aktiengesellschaft
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