Multiplier for binary numbers in two's-complement notation

Details Multiplier for binary numbers in two's-complement notation Multiplier for binary numbers in two's-complement notation

1981-07-13

1984-02-14

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

044320663

ABSTRACT:
A device for multiplying two binary numbers in two's-complement notation having an array for forming bit-wise partial products and a further array for successively forming the result bits therefrom. The modules of the further array form either a full adder or a full subtractor under the control of a one-bit control signal. The negative sign of the most-significant bits of the factors can thus be taken into account. Devices of this kind can be linked in order to realize multiplications with higher precision, variation of the control signal signalling that only the device to which a most significant factor bit is applied takes into account a negative sign. A pipe line product-accumulator device is formed by construction in n-MOS dynamic logic circuits, with an inherent trigger function on the outputs of full adders/subtractors.

REFERENCES:
patent: 3469086 (1969-09-01), Matthews, Jr.
patent: 3670956 (1972-06-01), Calhoun
patent: 3752971 (1973-08-01), Calhoun
patent: 3947670 (1976-03-01), Irwin et al.
patent: 4130878 (1978-12-01), Balph et al.

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