Multiplier circuit for multiplying an information signal by a pe

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375 24, H03C 100

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active

045176558

ABSTRACT:
Multiplier circuit for multiplying an information signal x(t) by a periodic signal y(t) having frequency f.sub.o, more specifically for amplitude modulation purposes in a stereo decoder. The multiplier circuit comprises N switching circuits 21(k) wherein k=0, 1, . . . N-1 which are each connected to a clock pulse generator 221, 222 by means of a control channel 25(k) and are each connected to an input of an adder device 28 by means of a signal channel 26(k). In addition, each switching circuit 21(k) receives the information signal x(t). A series of clock pulses g(k;t) is applied to each control channel in such a manner that for the control channel having number k these clock pulses occur at the instants t.sub.o +k(T.sub.o /N)+iT.sub.o wherein t.sub.o represents a constant T.sub.o =1/f.sub.o and i=. . . , -2, -1, 0, 1, 2, . . . Each signal channel 26(k) comprises a weighting network 27(k) having a constant weighting factor W(k) defined by the relation W(k)=y(t.sub.o +k(T.sub.o /N)). Each control channel 25(k) (or each signal channel 26(k)) incorporates a pulse reshaping circuit 24(k), which converts a pulse applied thereto into a pulse having a width equal to .tau.=T.sub.o /M wherein M represents an integer, for example M=N-1.

REFERENCES:
patent: 3611143 (1971-10-01), Van Gerwen Emmasingel
patent: 3869670 (1975-03-01), Grutzmann et al.
patent: 4300019 (1981-11-01), Toyomaki
patent: 4320361 (1982-03-01), Kikkert
patent: 4346354 (1982-08-01), Hanna

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