Multiplier circuit for multiplication operation between binary a

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

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708626, G06F 752

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active

061516171

ABSTRACT:
A multiplier circuit multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary factors, and a combinatorial network provides the final sum of the partial products. The partial multiplications that include at least one of the more significant bits of the operands are performed by logic gating circuits which can be enabled to also carry out a two's complement partial multiplication. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values unrelated to the factors.

REFERENCES:
patent: 4153938 (1979-05-01), Ghest et al.
patent: 5121352 (1992-06-01), Hesson
Roth, Jr. "Fundamentals of Logic Design" Second Edition, Chapter 8.4-8.6, pp. 164-170.
Paolo Montuschi and Luigi Ciminera, "n.times.n Carry-Save Multipliers without Final Addition," in Proc. 11th Symposium on Computer Arithmetic, IEEE Computer Society IEEE Technical Committee on VLSI, Windsor, Ontario, Canada, Jun. 29-Jul. 2, 1993, pp. 54-61.

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