Multiplier circuit for multiplication operation between binary a

Details Multiplier circuit for multiplication operation between binary a Multiplier circuit for multiplication operation between binary a

1995-12-22

1999-08-10

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708626, G06F 752

Patent

active

059352019

ABSTRACT:
A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.

REFERENCES:
patent: 4153938 (1979-05-01), Ghest et al.
patent: 5121352 (1992-06-01), Hesson
Montuschi, Paolo and Luigi Ciminiera, "n.times.n Carry-Save Multipliers without Final Addition," in Proc. 11.sup.th Symposium on Computer Arithmetic, IEEE Computer Society IEEE Technical Committee on VLSI, Windsor, Ontario, Canada, Jun. 29-Jul. 2, 1993, pp. 54-61.

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