Multiplier circuit design for a programmable logic device

Details Multiplier circuit design for a programmable logic device Multiplier circuit design for a programmable logic device

1996-02-08

1998-05-19

Elmore, Reba I.

Boots, shoes, and leggings

36476002, G06F 752

Patent

active

057544590

ABSTRACT:
The multiplier circuit has as input signals an M bit multiplicand and an N bit multiplier and outputs a M+N bit product. The multiplier circuit includes a number of recoder circuits. The recoder circuits recode the N bit multiplier into fewer bits, thereby reducing the longest signal path through the multiplier circuit and increasing the speed of the circuit. In one embodiment, the recoder circuits perform a N to N/2 Booth recoding. The recoder circuits are combined with other circuitry to generate partial products. The partial products are combined in a three to two compression circuit. The compression circuit further reduces the longest signal path through the multiplier circuit. In one embodiment, the three to two compression circuits are configured in a Wallace Tree. In another embodiment, four to two compression circuits are used. The compression circuit outputs two addends. The two addends are then added in an adder to generate the product. The recoder circuit and the first partial product circuits are configured within a single programmable logic element of the programmable logic device. Therefore, one embodiment of the invention efficiently uses the programmable logic elements of the programmable logic device.

REFERENCES:
patent: 4646257 (1987-02-01), Essig et al.
patent: 5251167 (1993-10-01), Simmonds et al.
patent: 5265043 (1993-11-01), Naini et al.
patent: 5465226 (1995-11-01), Goto
patent: 5473559 (1995-12-01), Makino
patent: 5504915 (1996-04-01), Rarick
"The Programmable Logic Data Book" 1994 edition, pp.2-5 to 2-25, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California.
The Abstract of Suthikshn Kumar, Kevin Forward and M. Palaniswami, "A Fast-Multiplier Generator for FPGAs", pp. 53-56, IEEE 8th International Conference on VLSI Design, Jan. 1995.
"XACT Step, Libraries Guide", 1995 edition, pp. 4-97 to 4-122, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California.
Jalil Gadavi-Ardekani, MxN Booth Encoded Multiplier Generator Using Optimized Wallace Trees, IEEE Transactions on VLSI Systems, pp. 120-125, Apr. 1993.

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