Multiplier circuit

Details Multiplier circuit Multiplier circuit

1989-05-15

1991-08-06

Malzahn, David H.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

050383159

ABSTRACT:
In a multiplier for binary numbers represented in two's complement notation, the need to perform sign-bit extension in order to combine the partial products is avoided by representing the value represented by the sign bits of all the partial products as a two's complement number in its own right. The bits of that number, rather than the original sign bits, are then used in the partial product addition. Since (as with all two's complement numbers) all the bits of the sign-bit-value word are guaranteed to have positive significance (except for the left-most one), the digits of the partial products can then be direcly added without the need for sign bit extension.

REFERENCES:
patent: 3627999 (1971-12-01), Iverson
patent: 3761699 (1973-09-01), Sather
patent: 4538239 (1985-08-01), Magar
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4748582 (1988-05-01), New et al.
patent: 4791601 (1988-12-01), Tanaka
patent: 4868778 (1989-09-01), Disbrow

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