Multiplier circuit

Details Multiplier circuit Multiplier circuit

1991-11-05

1992-09-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307529, 328160, G06G 712, G06G 700, G06G 716

Patent

active

051516241

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention relates to a multiplier circuit.
Analog multiplier circuits which have two analog inputs, form a product of the two input signals and forward this product to an analog output are frequently required in signal processing. Multiplier circuits--whether employing analog or digital circuitry--are components which are known and frequently used. For instance, an emitter-coupled transistor pair can be cited here as a very simple realisation of an analog multiplier circuit (cf. Gray, Meyer, "Analysis and Design of Analog Integrated Circuits", Second Edition, John Wiley and Sons, 1984, on pages 590 to 593). In FIG. 10.6 of this publication the base terminals and the common emitter terminal, respectively, of the transistor pair form the two analog inputs and the collector terminals form the outputs of an analog multiplier.
Analog multiplier circuits are employed, for instance, as a phase detector or in frequency doubling circuits. As a phase detector, the multiplier circuit is intended to supply an output voltage proportional to the phase difference at the input, and this up to as high a frequency as possible. Given a phase difference of 90.degree. at both inputs, the output voltage of the phase detector should lie in the middle of the modulation range. This corresponds to a phase error of zero. The modulation range of the phase detector should be 180.degree.. In addition to an analog multiplier circuit, a frequency doubler also contains a 90.degree. phase shifter in order to be able to achieve an effective frequency doubling in large-signal operation in the case of sinusoidal input signals with equal phase. It should also be able to supply true push-pull signals up to the highest frequencies.
A Gilbert cell is frequently employed in the present state of the art as a multiplier circuit for phase detection or frequency doubling. The design and the use of such a Gilbert cell can be found in the above-mentioned publication by Gray, Meyer: "Analysis and Design of Analog Integrated Circuits" on pages 593 to 605. In the case of digital input signals, the Gilbert cell here provides an XOR gating as a logic function. The suitability of this circuit in the case of frequencies close to the limiting frequency of the bipolar transistors is lessened by the different transit times in the lower and upper circuit level of the Gilbert cell. Given a different number of additional upstream level-shift stages in the lower and the upper circuit level of the Gilbert cell, besides an additional transit time as a result of the differential stage in the lower circuit level, a further transit time as a result of the different number of level-shift stages is produced as the total transit time difference between the input signals of the upper and lower circuit level. When employed as a phase detector this asymmetry leads to a phase error which rapidly increases as the frequency rises and greatly reduces the symmetry of the output characteristic around the mid-position at 90.degree.. In the case of a frequency doubling circuit the same transit time effect leads to an alteration of the amplitude ratios of the push-pull outputs.


SUMMARY OF THE INVENTION

The object of the invention is to disclose a multiplier circuit which has a symmetrical characteristic given a 90.degree. phase difference of the input signals even for high frequencies when employed as a phase detector, and does not lead to any alteration of the amplitude ratios at the push-pull outputs at high frequencies when employed in a frequency doubling circuit.
The particular advantages conferred by the invention are that the limiting frequency of the multiplier circuit according to the invention is no longer limited by the phase error, but solely by the switching time of the bipolar transistors; it is therefore higher than in conventional multiplier circuits. For all frequencies below the limiting frequency, given a phase difference of 90.degree. the output signal lies exactly in the middle of the modulation range.


BRIEF DESCRIPTION OF THE D

REFERENCES:
patent: 4353000 (1982-10-01), Noda
patent: 4870303 (1989-07-01), McGinn
"Analysis and Design of Analog Integrated Circuits" Grey, Meyer, Second Edition, John Wiley & Sons, 1984, pp. 590-605.
"Monolithic Analog Multiplier-Divider", Johan H. Juijsing, et al, IEEE Journal of Solid-State Circuits, vol. Sc-17, No. 1, Feb. 1982, pp. 9-15.

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