Multiplier circuit

Details Multiplier circuit Multiplier circuit

1995-11-22

1998-05-05

Ngo, Chuong Dinh

Boots, shoes, and leggings

36476003, G06F 752

Patent

active

057485178

ABSTRACT:
It is an object to obtain a multiplier circuit with reduced circuit scale or with reduced power consumption. Booth decoders (BD1-BD3) receive overlapping three bits of a 6-bit multiplier (Y) (Y0-Y5), respectively, and output partial product information groups (S1-S5) to partial product generating circuits (PP1-PP3) on the basis of the three bits of the multiplier (Y), respectively. Each partial product information is provided in a one-to-one correspondence for each kind of partial product. The partial product generating circuits (PP1-PP3) respectively receive the partial product information groups (S1-S5) from the respective Booth decoders (BD1-BD3) and a 8-bit multiplicand (X) (X0-X7), and output partial products (SM1-SM3) to a partial product adder circuit (ADD1). The partial product adder circuit (ADD1) adds the partial products (SM1-SM3) and outputs a multiplication result (XY) of the multiplier (Y) and the multiplicand (X).

REFERENCES:
patent: 5231415 (1993-07-01), Hagihara
patent: 5235536 (1993-08-01), Matsubishi et al.
patent: 5235538 (1993-08-01), Sumi et al.
patent: 5251167 (1993-10-01), Simmonds et al.

Affiliated with

Also associated with

Rating

Multiplier circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiplier circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplier circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-62384