Multiplier array processing system with enhanced utilization at

Details Multiplier array processing system with enhanced utilization at Multiplier array processing system with enhanced utilization at

1997-05-16

1999-09-14

Powell, Mark R.

Boots, shoes, and leggings

36473602, 364757, 364758, 36476003, 3647505, 36472416, 39580009, 39580035, G06F 748, G06F 752

Patent

active

059532416

ABSTRACT:
A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.

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patent: 4969118 (1990-11-01), Montoye et al.
patent: 5032865 (1991-07-01), Schlunt
patent: 5408581 (1995-04-01), Suzuki et al.
patent: 5500811 (1996-03-01), Corry

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