Multiplier and shift device using signed digit representation

Details Multiplier and shift device using signed digit representation Multiplier and shift device using signed digit representation

2007-08-14

2007-08-14

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S420000

Reexamination Certificate

active

10399178

ABSTRACT:
The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder in connection with the multiplication which contributes to a reduced hardware amount and reduced required area for the hardware. A shifter means based on binary weighted shifting is used for shifting in connection with the multiplication, thereby reducing the required hardware amount (number of multiplexers and hardwired shifting elements) and thus reducing the area for hardware implementation still further. The present invention can be used in applications using digital multiplication, such as in digital signal processing DSP, digital filters and/or finite impulse response filters FIR filters as well as programmable and/or adaptive digital filters. As the multiplier is represented in CSD coding, the number of necessary shifting operations can be reduced and the number of necessary additions can be reduced, thus contributing to a reduced area needed for a hardware realization of a shifting means and a multiplier device on a silicon chip.

REFERENCES:
patent: 4546446 (1985-10-01), Machida
patent: 4947364 (1990-08-01), Mahon et al.
patent: 4967388 (1990-10-01), Tate
patent: 5253195 (1993-10-01), Broker et al.
patent: 5262974 (1993-11-01), Hausman et al.
patent: 5465222 (1995-11-01), Seckora
patent: 5483477 (1996-01-01), Sato et al.
patent: 5978822 (1999-11-01), Muwafi et al.
patent: 6590931 (2003-07-01), Wittig
patent: 2003/0220956 (2003-11-01), Parhi et al.
patent: 2004/0170223 (2004-09-01), Chiueh et al.
K. Parhi, A Systematic Approach For Design Of Digit-Serial Signal Processing Architectures, IEEE Transactions On Circuits And Systems, vol. 38, No. 4, Apr. 1991, pp. 358-375.
Oh et al., Implementation of Programmable Multiplierless FIR Filters With Powers-of-Two Coefficients, IEEE Transactions On Circuits And Systems-II: Analog and Digital and Signal Processing, vol. 42, No. 8, Aug. 1995, pp. 553-558.
Duan, et al., Versatile Beamforming ASIC Architecture For Broadband Fixed Wireless Access, IEEE 1999 Custom Integrated Circuits Conference; Electrical Engineering Department, University of California, Los Angeles, pp. 545-548.
Duan, et al., A Highly Versatile Beamforming ASIC for Application in Broad-Band Fixed Wireless Access System, IEEE Journal of Solid-State Circuits, vol. 35, No. 3, Mar. 2000, pp. 391-400.
Khoo, et al., A Programmable FIR Digital Filter Using CSD Coefficients, IEEE Journal of Solid-State Circuits, vol. 32, No. 6, Jun. 1996, pp. 869-874.
Chang, et al., Systematic Design Of High-Speed and Low-Power Digit-Serial Multipliers, IEEE Transactions On Circuits And Systems-II: Analog and Digital and Signal Processing, vol. 45, No. 12, Dec. 1998, pp. 1585-1596.

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