Multiplier and arithmetic unit for calculating sum of product

Details Multiplier and arithmetic unit for calculating sum of product Multiplier and arithmetic unit for calculating sum of product

1999-08-30

2004-03-09

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S625000, C708S630000

Reexamination Certificate

active

06704762

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiplier and an arithmetic unit for calculating a sum of products, both of which are preferred to apply to a processor.
2. Description of the Related Art
General-purpose processors, in recent years, mostly tend to include a multiplier applying partial product generation with using a Booth's algorithm and partial product addition by means of a carry save method. For relatively low cost processors for computers, there has been a great increase in the proportion of multiplication operations with a low degree of accuracy, in terms of approximately sixteen bits, mainly for signal processing, for example, image processing or the like, in addition to multiplication operations with a high degree of accuracy, in terms of thirty two or sixty four bits.
For the sake of reduction in the number of parts embodied in the calculation systems, recently, general-purpose processors are intended to carry out signal processing, which has conventionally been executed by a special-purpose processor, such as a DSP (Digital Signal Processor), etc. This means that the general-purpose processors need to have a function for executing a multiplication operation with a low degree of accuracy, in terms of sixteen bits. Because the large amount of data is handled in the signal processing, such as the image processing or the like, processors for performing such signal processing are required to have a function for executing a multiplication operation with a low degree of accuracy with high efficiency.
FIG. 8
illustrates the first example of a multiplier according to the conventional techniques. The multiplier shown in
FIG. 8
comprises two multipliers
801
a
and
801
b
for performing multiplication operations with “sixteen bit accuracy”, a sixty four bit adder
802
, a sixty four bit register
803
, selectors
804
a
,
804
b
, and an input selector
805
for sending data to an adder
804
.
In this multiplier, thirty two bit data A including the sixteen most significant bits (a
1
) and the sixteen least significant bits (a
2
), and thirty two bit data B including the sixteen most significant bits (b
1
) and the sixteen least significant bits (b
2
) are given as input data. In a case of performing two multiplication operations with the “sixteen bit accuracy”, in the multiplier, each set of the bits a
1
, a
2
, b
1
, and b
2
is assumed as independent sixteen bit data. In this case, data including combinations of (a
1
, b
1
) and (a
2
, b
2
) are supplied to a corresponding one of the sixteen bit multipliers
801
a
and
801
b
, respectively, by controlling the selectors
804
a
and
804
b
. Now, each of the multipliers
801
a
and
801
b
concurrently outputs corresponding solution of (a
1
×b
2
) and (a
2
×b
2
) each as a multiplication result thereof.
In a case of performing a multiplication operation for calculating (A×B) with “thirty two bit accuracy”, the multiplier makes the multipliers
801
a
and
801
b
calculate (a
1
×b
2
) and (a
2
×b
1
) by controlling the selectors
804
a
and
804
b
. The adder
802
adds the calculation results and generates an intermediate result (a
1
×b
2
+a
2
×b
1
), and stores the generated result in the register
803
. Now, the multiplier makes the multiplier
801
a
calculate (a
1
×b
1
), and makes the selector
805
output the value stored in the register
803
. The adder
802
adds the output from the multiplier
801
a
and the output from the selector
805
, and stores its resultant addition (a
1
×b
2
+a
2
×b
1
+a
1
×b
1
) in the register
803
as a new intermediate result. The adder
802
adds the new intermediate result with a multiplication result (a
2
×b
2
), and outputs the ultimate multiplication result (a
1
×b
2
+a
2
×b
1
+a
1
×b
1
+a
2
×b
2
).
The multiplier shown in
FIG. 8
may carry out two multiplication operations with the “sixteen bit accuracy” as well as a multiplication operation with “thirty two bit accuracy”. However, in the conventional multipliers, problematic performance is recognized in that multiplication operations are performed with low efficiency (especially, in the calculation time) with the “thirty two bit accuracy”, since the multipliers need to generate an intermediate result at least twice in the case of performing the multiplication operation with the “thirty two bit accuracy”.
FIG. 9
illustrates the second example of a conventional multiplier. The multiplier shown in
FIG. 9
comprises a “thirty two bit” multiplier
901
, and two “sixteen bit” multipliers
902
a
and
902
b
. The conventional multiplier has such a structure so as to simultaneously execute two multiplication operations with the “sixteen bit accuracy”, and execute a multiplication operation with the “thirty two bit accuracy” at high speed. However, in such a conventional multiplier, a problematic matter arises in that hardware becomes large in its scale, for the multiplier needs to include a multiplier with high accuracy, in addition to two multipliers with low accuracy.
As disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H7-121354, a multiplier performs multiplication operations with high accuracy (double accuracy), multiplication operations with low accuracy (single accuracy), and calculations for obtaining inner products, and further multiplication operations for multiple prime numbers, by modifying a Booth's algorithm. However, in this multiplier, a problematic matter arises in that no means for simultaneously executing multiplication operations with low accuracy is included, so that it is required a calculation time as the same as executing multiplication operations with high accuracy, for executing a set of multiplication operations with the low accuracy.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a multiplier capable of executing multiplication operations with high accuracy at high speed, capable of executing a plurality of multiplication operations with low accuracy, and capable of attaining reduction of hardware scale.
Another object of the present invention is to provide an arithmetic unit, for calculating a sum of products, capable of executing a plurality of calculations with low accuracy, and capable of calculating a sum of products at high speed.
In order to achieve the above-described objects, according to the first aspect of the present invention, there is provided a multiplier for executing a multiplication operation using a Booth's algorithm, comprising:
a Booth decoder which divides a multiplier (Y) into a plurality of partial bit rows and outputs the divided bit rows;
a first multiplier replacing circuit which replaces, with “0”, a value of a most significant bit (Y
3
) included in least significant half of bits of the multiplier (Y) in accordance with a first control signal (SIMD), so as to replace, with “0”, a predetermined bit included in the plurality of bit row;
a plurality of partial product generating circuits each of which is arranged in a manner corresponding to each corresponding one of the partial bit rows divided by the Booth decoder, and generates a partial product, represented in bits which are twice as many as a bit number of a multiplicand, of the multiplicand (X) and each corresponding partial bit row;
a first adder which adds bit rows including the least significant half of bits of the partial products generated by the plurality of partial product generating circuits;
a second adder which adds bit rows including most significant half of bits of the partial product generated by the plurality of partial product generating circuits, in consideration of one or more carry signals; and
a carry selecting circuit which selects either a bit row composed of “0” or one or more carry signals which the first adder outputs, in accordance with the first control signal (SIMD), and supplies, to the second adder, the selected data as one or more carry signals;
wherei

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