Multiplier/adder circuit

Details Multiplier/adder circuit Multiplier/adder circuit

1981-04-01

1983-12-20

Ruggiero, Joseph F.

Boots, shoes, and leggings

364844, 381 51, G06J 100

Patent

active

044221550

ABSTRACT:
This invention provides a uniquely designed switched capacitor multiplier/adder (129) which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit results in a significant reduction in space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This reduction in size results in a significant reduction in the manufacturing costs for this circuit over prior art circuits, and additionally allows the option of including on the speech synthesis chip a memory for the storage of binary representations of to-be-synthesized speech patterns.

REFERENCES:
patent: 3309508 (1967-03-01), Witt
patent: 3484589 (1969-12-01), Jernakoff
patent: 3634659 (1972-01-01), Lucas et al.
patent: 3683165 (1972-08-01), Grobert et al.
patent: 4126852 (1978-11-01), Baertsch

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