Multiplier-accumulator circuit using latched sums and carries

Details Multiplier-accumulator circuit using latched sums and carries Multiplier-accumulator circuit using latched sums and carries

1984-11-13

1988-04-05

Malzahn, David H.

Boots, shoes, and leggings

364754, 364748, G06F 752

Patent

active

047363355

ABSTRACT:
Vector dot multiplication is facilitated in a multiplier in which pipelining techniques are employed. Two vectors u(i), v(i), each having the same number of components (L), the components of the vector u(i) having m bits, and the components of the other vector v(i) having n bits per component. For example, a classical positive integer dot multiplier includes m-1 multiplier rows with each multiplier row having n+1 multiplying stages, each stage including an adder and latches. A latch interconnects the carry-out of each adder in a row to the carry-in of another adder in the same row, and a latch interconnects the sum output of each adder in a row to an input of another adder in another row. The result is accumulated in an adder according to the length of the vectors to be processed. 2's compliment number multiplication is accommodated by stretching each multiplier row by connecting two full adders serially therewith. Additionally, an inverter inverts the words u(i) and then applies the inverted words to the last multiplier row along with the sign bit for the other vector v(i). The same concept may be used to implement a variety of multipliers and floating point dot multipliers.

REFERENCES:
patent: 3794820 (1974-02-01), Robinson
patent: 4354249 (1982-10-01), King et al.
patent: 4432066 (1984-02-01), Benschop
patent: 4511990 (1985-04-01), Hagiwara et al.
patent: 4525796 (1985-06-01), Omoda et al.
patent: 4589067 (1986-05-01), Porter et al.
patent: 4616330 (1986-10-01), Betz

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