Boots – shoes – and leggings
Patent
1984-07-06
1987-07-07
Williams, Jr., Archie E.
Boots, shoes, and leggings
G06F 754
Patent
active
046791655
ABSTRACT:
A multiplication unit for n-place binary numbers has a first register containing the multiplicand, and accumulator, and an arithmetic unit having operand inputs connected to the first register and to the accumulator. The operation to be undertaken by the arithmetic unit is to find by the bits of a multiplier which is contained in a second register, the second register being connected to an operation instruction input of the arithmetic unit. A multiplexer having inputs connected to the outputs of the second register through-connects the bits of five adjacent multiplier places to the inputs of a logic circuit, which derives the operation instruction for the arithmetic unit. The logic circuit also supplies an instruction to a mulitple shift unit interconnected between the output of the arithmetic unit and the input of the accumulator.
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patent: 4589086 (1986-05-01), Beifuss et al.
Digitale "Rechenanlagen", Speiser, pp. 184-187, 1965.
"Introduction to VLSI Systems", Mead et al., pp. 157-162, 1980.
Shaw Dale M.
Siemens Aktiengesellschaft
Williams Jr. Archie E.
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