Multiplication logic circuit

Details Multiplication logic circuit Multiplication logic circuit

2006-11-21

2006-11-21

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S210000

Reexamination Certificate

active

07139788

ABSTRACT:
A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.

REFERENCES:
patent: 3634658 (1972-01-01), Brown
patent: 3757098 (1973-09-01), Wright
patent: 4399517 (1983-08-01), Niehaus et al.
patent: 4607176 (1986-08-01), Burrows et al.
patent: 5095457 (1992-03-01), Jeong
patent: 5175862 (1992-12-01), Phelps et al.
patent: 5187679 (1993-02-01), Vassiliadis et al.
patent: 5325320 (1994-06-01), Chiu
patent: 5343417 (1994-08-01), Flora
patent: 5497342 (1996-03-01), Mou et al.
patent: 5524082 (1996-06-01), Horstmann et al.
patent: 5701504 (1997-12-01), Timko
patent: 5978827 (1999-11-01), Ichikawa
patent: 5995029 (1999-11-01), Ryu
patent: 6023566 (2000-02-01), Belkhale et al.
patent: 6490608 (2002-12-01), Zhu
patent: 6938061 (2005-08-01), Rumynin et al.
patent: 2002/0026465 (2002-02-01), Rumynin et al.
patent: 2002/0078110 (2002-06-01), Rumynin et al.
patent: 2004/0103135 (2004-05-01), Talwar
patent: 2004/0153490 (2004-08-01), Talwar et al.
patent: 0168650 (1986-01-01), None
patent: 0309292 (1989-03-01), None
patent: 0442356 (1991-08-01), None
patent: 0741354 (1996-11-01), None
patent: 2475250 (1981-08-01), None
patent: 2016181 (1979-09-01), None
patent: 2062310 (1981-05-01), None
patent: 2365636 (2002-02-01), None
patent: 2365637 (2002-02-01), None
patent: WO-99/22292 (1999-05-01), None
patent: WO-02/12995 (2002-02-01), None
Chakraborty, S. , et al., “Synthesis of Symmetric Functions for Path-Delay Fault Testability”,12th International Conference on VLSI Design, (1999),pp. 512-517.
Debnath, D. , “Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing”,IEICE Trans. Inf.&Syst., E80-D, 10, (1997),pp. 1001-1008.
Drechsler, R. , et al., “Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions”,IEEE, (1995),pp. 91-97.
Goto, et al., “A 54×54-b Regularly Structured Tree Multiplier”,IEEE Journal of Solid-State Circuits, vol. 27, No. 9, (Sep. 1992),1229-1236.
Hekstra, et al., “A Fast Parallel Multiplier Architecture”,IEEE International Symposium on Circuits and Systems; Institute of Electrical and Electronic Engineers, c1977-c1996, 20v. :ill. :28cm, (1992),2128-2131.
Nienhaus, H. , “Efficient Multiplexer Realizations of Symmetric Functions”,IEEE, (1981),pp. 522-525.
Oklobdzija, V G., et al., “Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology”,IEEE transactions on Very Large Scale Integration(VLSI)Systems, IEEE, Inc, New York, vol. 3, No. 2,(1995),292-301.
Vassiliadis, S. , et al., “7/2 Counters and Multiplication with Threshold Logic”,IEEE, (1997),pp. 192-196.
Zuras, D , et al., “Balanced delay trees and combinatorial division in VLSI”,IEEE Journal of Solid State Circuits, SC-21, IEEE Inc, New York, vol. SC-21, No. 5,(1986),814-819.
PCT International Search Report for corresponding application No. PCT/GB02/01343, international filing date Mar. 21, 2002, mailing date Dec. 27, 2002, four pages.
Booth, A.D., “A Signed Binary Multiplication Technique”,Oxford University Press, Reprinted from Q.J. Mech. Appl. Math. 4:236-240, pp. 100-104, (1951).
Dadda, L., “On Parallel Digital Multipliers”,Associazione Elettrontecnia ed Elettronica Italiana, Reprinted from Alta Freq. 45:574-580, pp. 126-132, (1976).
Dadda, L., “Some Schemes For Parallel Multipliers”,Assocciazione Elettrotenica ed Elettronica Italiana, Reprinted from Alta Freq. 34:349-356, pp. 118-125, (1965).
Fleisher, H., “Combinatorial Techniques for Performing Arithmetic and Logical Operations”,IBM Research Center, RC-289, Research Report, pp. 1-20, (Jul. 18, 1960).
Foster, C.C., et al., “Counting Responders in an Associative Memory”,The Institute of Electrical and Electronics Engineers, Inc.,Reprinted, with permission, from IEEE Trans. Comput. C-20:1580-1583, pp. 86-89, (1971).
Ho, I.T., et al., “Multiple Addition by Residue Threshold Functions and Their Representation By Array Logic”,The Institute of Electrical and Electronics Engineers, Inc.,Trans. Comput. C-22: 762-767, pp. 80-85, (1973).
Jones, R.F., et al., “Parallel Counter Implementation”,Conf. Rec. 26th Asilomar Conf. Signals, Systems&Computers, vol. 1, ISBN 0-8186-3160-0, pp. 381-385, (1992).
Swartzlander, Jr., E.E., “Parallel Counters”,Institute of Electrical and Electronic Engineers, Inc., Reprinted, with permission from IEEE Trans. Comput.,C-22:1021-1024, pp. 90-93, (1973).
Wallace, C.S., “A Suggestion for a Fast Multiplier”,The Institute of Electrical and Electronics Engineers, Inc.,Reprinted, with permission, from IEEE Trans. Electron. Comput. EC-13:14-17, pp. 114-117, (1964).
“Communication Pursuant to Article 96(2) EPC, for Application No. EP 02 722 402.1, date mailed Jun. 6, 2005”, 3 Pages.
Nicholson, J.O., “Parallel-Carry Adders Listing Two-Bit Covers”,IBM Technical Disclosure, Bulletin, 22(11),(Apr. 1980), 5036-5037.
Ong, S., et al., “A Comparision of ALU Structures for VLSI Technology”,Proceedings, 6th Symposium on Computer Arithmetic (IEEE),(1983), 10-16.
Schmookler, M. S., et al., “Group-Carry Generator”,IBM Technical Disclosure Bulletin,6(1), (Jun. 1963), 77-78.
Song, Paul J., et al., “Circuit and Architecture Trade-offs for High-Speed Multiplication”,IEEE Journal of Solid-State Circuits, vol. 26, No. 9,(Sep. 1991), 1184-1198.
Weinberger, A., “Extension of the Size of Group Carry Signals”,IBM Technical Disclosure Bulletin, 22(4),(Sep. 1979), 1548-1550.
Weinberger, A., “Improved Carry-Look-Ahead”,IBM Technical Disclosure Bulletin,21(6), (Nov. 1978), 2460-2461.

Affiliated with

Also associated with

Rating

Multiplication logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiplication logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplication logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3644314