Multiplication, division and square root extraction apparatus

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364752, G06F 700, G06F 738

Patent

active

059562633

ABSTRACT:
A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

REFERENCES:
patent: 3631230 (1971-12-01), Chen
patent: 4477879 (1984-10-01), Wong
patent: 4878190 (1989-10-01), Darley et al.
patent: 4901267 (1990-02-01), Birman et al.
patent: 4999801 (1991-03-01), Katsuno

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