Multiplication device using semiconductor memory

Details Multiplication device using semiconductor memory Multiplication device using semiconductor memory

1995-06-05

1997-04-01

Gordon, Paul P.

Boots, shoes, and leggings

364754, G06F 752

Patent

active

056173466

ABSTRACT:
The present invention discloses a multiplication device. A multiplicand X of eight bits and a multiplier Y of eight bits are input and a product P of sixteen bits is found from these multiplication factors. MULTIPLICAND X is divided into two parts, an upper-order part X.sub.U of four bits and a low-order part X.sub.L of four bits. MULTIPLIER Y is likewise divided into two parts, an upper-order part Y.sub.U of four bits and a low-order part Y.sub.L of four bits. Thereafter, four 8-bit partial products, i.e., X.sub.L .times.Y.sub.L, X.sub.L .times.Y.sub.U, X.sub.U .times.Y.sub.L, and X.sub.U .times.Y.sub.U are computed one after another. These partial products are subjected to a digit place alignment addition operation, by an adder, to compute PRODUCT P. Computation of each of the partial products is implemented by performing addition of an approximate partial product AP retrieved by a 6-bit address from a 64-byte ROM, and a correction value H and a carry C generated by a correction value generator.

REFERENCES:
patent: 5117385 (1992-05-01), Gee
patent: 5379244 (1995-01-01), Miyoshi

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