Boots – shoes – and leggings
Patent
1996-02-14
1997-10-07
Mai, Tan V.
Boots, shoes, and leggings
364759, 3647505, G06F 752, G06F 700
Patent
active
056755279
ABSTRACT:
In the first half of one cycle of a clock, a partial product generation circuit of each stage in a multiplication array generates partial products on the basis of one bit of the 16 low-order bits of multiplier data and the bits of multiplicand data. An accumulative addition circuit of each stage in the multiplication array accumulatively adds an initial value or an output from a previous accumulative addition circuit to the partial products to perform half necessary multiplication, writes the accumulative result in a latch as intermediate result data, and writes the predetermined number of bits of an output from the accumulative addition circuit of each stage at a predetermined bit position of the latch. In the second half of the clock, the partial product generation circuit of each stage generates partial products on the basis of one bit of an output from a latch holding the 16 high-order bits of a multiplier and the bits of the multiplicand data. In addition, the accumulative addition circuit of each stage accumulatively adds the intermediate result data or an output from a previous accumulative addition circuit to the partial products to perform the remaining half the calculation, and writes the final accumulative addition result and the predetermined number of bits of the output from the accumulative addition circuit of each stage in a latch.
REFERENCES:
patent: 4811269 (1989-03-01), Hirose et al.
IBM Tech. Discl. vol. 23, No. 9 Feb. 1981, pp. 4322-4323, Chevillat et al. "Pipelined Hardware Multiplier with Extended Precision".
Nagamatsu et al., "A 150MIPS/W CMOS RISC Processor for PDA Applications", Session Digital Design Elements, pp. 114-115, (1995).
Kabushiki Kaisha Toshiba
Mai Tan V.
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