Multiplication circuit using column compression

Details Multiplication circuit using column compression Multiplication circuit using column compression

1978-02-13

1979-09-18

Malzahn, David H.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

041685300

ABSTRACT:
A high speed parallel operation, multiplication circuit is provided having a multiplier multiplexor which may function in combination with a column compressor for providing a resultant product, wherein, preferably, the multiplier multiplexor has been implemented using a modified Booth's algorithm, and wherein the column compressor operates to process every column within the same propagation delay whereby every input may create an output in essentially the same propagation time, i.e., true parallel operation requiring preferably no more than an average column propagation delay time.

REFERENCES:
patent: 3515344 (1970-06-01), Goldschmidt et al.
patent: 3691359 (1972-09-01), Dell et al.
patent: 3761698 (1973-09-01), Stephenson
patent: 3795880 (1974-03-01), Singh et al.
patent: 4041292 (1977-08-01), Kindell

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