Boots – shoes – and leggings
Patent
1997-01-27
1998-11-10
Mai, Tan V.
Boots, shoes, and leggings
G06J 100
Patent
active
058353879
ABSTRACT:
Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X.sub.i corresponding to each element of the first input data string is input to capacitance switching circuits 10.sub.1 to 10.sub.n through input terminals 1.sub.1 to 1.sub.n. m bit of digital control data A.sub.i corresponding to each element of the second input data string are input to each capacitance switching circuit 10.sub.i, and each bit a.sub.j of the control signal A.sub.j is input to the corresponding multiplexer circuit 6.sub.ij. In the multiplexer circuit 6.sub.ij, the capacitances C.sub.ij corresponding to the value of each bit of the control signal a.sub.j are connected to the input terminal 1.sub.i or the reference charge V.sub.STD. The voltages corresponding to the products of inputted analog voltages X.sub.1 and the control signals A.sub.i are outputted from each capacitance switching circuit 10.sub.j. The output voltages of each capacitance switching circuit 10.sub.i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.
REFERENCES:
patent: 5361219 (1994-11-01), Shou et al.
patent: 5381352 (1995-01-01), Shou et al.
patent: 5396442 (1995-03-01), Shou et al.
Motohashi Kazunori
Shou Gouliang
Takatori Sunao
Yamamoto Makoto
Mai Tan V.
Sharp Kabushiki Kaisha
Yozan Inc.
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