Boots – shoes – and leggings
Patent
1997-09-04
1999-10-05
Maung, Zarni
Boots, shoes, and leggings
36474811, 36474814, 36474809, 36474813, 36473605, 36473604, 36471508, 36471504, 39580042, 39580034, G06F 738
Patent
active
059634618
ABSTRACT:
A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles accumulate with no instructions started, subsequent fast instructions are executed by the fast execution path. A floating point multiplier is provided in which normalization/denormalization shift amounts are generated in parallel with multiplication of the significands of the operands. A floating point multiplier is provided in which the result is rounded in parallel with multiplication of the significands of the operands.
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Gorshtein Valery Y.
Khlobystov Vladimir T.
Maung Zarni
Shenker Michael
Sun Microsystems Inc.
Thomson William D.
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