Multiplexing system for a solid state timing device

Details Multiplexing system for a solid state timing device Multiplexing system for a solid state timing device

1979-08-15

1981-07-21

Miska, Vit W.

Horology: time measuring systems or devices

Chronological

With electro-optical display

307270, 340802, G04C 1900, H03K 301, G08B 522

Patent

active

042802121

ABSTRACT:
A CMOS timing device having a primary oscillatory reference source, a chain of series connected bistable divider stages whose data outputs are applied to a decoder/display by way of a multiplexing network. The multiplexing network is comprised of a plurality of multiplex sections, each section having a plurality of data transmission channels or paths. Each channel includes a plurality of MOS devices of a first type connected to a common bus. All channels driving the common bus share a single MOS device of a second type which provides a complementary function with respect to the first type to establish predetermined operating voltage levels for the data logic states carried by the common bus. The data on the common bus of each multiplex section is stored in a CMOS bistable latching type flip-flop whose regenerative feedback path is MOS device controlled.

REFERENCES:
patent: 3961472 (1976-06-01), Biehl
patent: 4019178 (1977-04-01), Hashimoso et al.
patent: 4024512 (1977-05-01), Amelio et al.
patent: 4063409 (1977-12-01), Batliss
patent: 4083175 (1978-04-01), Petropoulos et al.
patent: 4084402 (1978-04-01), Moyer
patent: 4121203 (1978-10-01), Edwards et al.

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