Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-04-23
2004-07-20
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S211000, C257S758000
Reexamination Certificate
active
06765295
ABSTRACT:
BACKGROUND
A complex integrated circuit is constructed of a plurality of interconnected layers. Typically, a poly-silicon layer containing logic circuitry utilizes one or more metal layers for interconnectivity, particularly where a signal requires a path of lower resistance instead of traversing across the poly-silicon layer. The metal layers have contacts on inner surfaces that mate with adjoining layers to complete inter-layer electrical circuits.
The inter-layer electrical circuits create certain design complexities during the design phase of the integrated circuit. More particularly, in the design phase, the integrated circuit is divided into blocks, each block providing certain design functionality. For example, a first block may provide memory cache functionality, and a second block may provide arithmetic processing functionality. These blocks often utilize one or more metal layers of the integrated circuit design. Circuitry within the first block then interacts with circuitry of the second block, requiring signal routing therebetween and across a first metal layer. This routing may require that a trace route through a third block in order to reach the second block; however, if one trace is already routed through the third block, it may not be possible to route a second trace through that third block if the second trace crosses the first trace on the first metal layer. Accordingly, the second trace is then routed through a second metal layer of the integrated circuit on order to reach its destination in the second block. This routing creates certain difficulties in the construction of the integrated circuit as extra connectors are required, increasing complexity and congestion in lower metal layers and increasing the size and cost of the final integrated circuit.
SUMMARY
In one aspect, a system multiplexes signals on a single metal layer of an integrated circuit of the type constructed from a poly-silicon layer and at least a first metal layer. A common trace exists with the first metal layer. First and second multiplexing circuits connect and disconnect a first signal of the integrated circuit to and from the common trace. Third and fourth multiplexing circuits connect and disconnect a second signal of the integrated circuit to and from the common trace. The multiplexing circuits respond to a control signal such that the first and second multiplexing circuits connect the first signal to the common trace when the third and fourth multiplexing circuits disconnect the second signal from the common trace, and such that the first and second multiplexing circuits disconnect the first signal from the common trace when the third and fourth multiplexing circuits connect the second signal to the common trace.
In another aspect, the first, second, third and fourth multiplexing circuits are disposed with the poly-silicon layer; a plurality of connectors couple between the first, second, third and fourth multiplexing circuits and the first metal layer.
In one aspect, the control signal is a common clock signal of the integrated circuit. Those skilled in the art appreciate that the control signal may be separately generated to control the multiplexing circuits in like manner.
In another aspect, an apparatus multiplexes signals across a common trace (e.g., within a printed circuit board or within an integrated circuit). First and second multiplexing circuits connect and disconnect a first signal to and from the common trace. Third and fourth multiplexing circuits connect and disconnect a second signal to and from the common trace, the multiplexing circuits respond to a control signal such that the first and second multiplexing circuits connect the first signal to the common trace when the third and fourth multiplexing circuits disconnect the second signal from the common trace and such that the first and second multiplexing circuits disconnect the first signal from the common trace when the third and fourth multiplexing circuits connect the second signal to the common trace.
In one example, a printed circuit board includes the apparatus, with the common trace being constructed within a single layer of the printed circuit board. The multiplexing circuits are for example constructed and arranged with the single layer or with another layer of the printed circuit board.
In another example, an integrated circuit includes the apparatus. The integrated circuit has a poly-silicon layer and one or more metal layers. The common trace is constructed within a single metal layer of the integrated circuit. The multiplexing circuits are constructed and arranged within the poly-silicon layer.
In yet another aspect, a method multiplexes a first signal and a second signal across a common trace, including the steps of: activating or deactivating a first pair of multiplexing circuits electrically coupled with the common trace; and activating or deactivating a second pair of multiplexing circuits electrically coupled with the common trace, such that only one of the first and second signals couples with the common trace at any one time.
As appreciated by those skilled in the art, any number of additional signals may be coupled across the common trace. By way of example, the method may include the further step of activating or deactivating one or more additional pairs of multiplexing circuits electrically coupled with the common trace to multiplex one or more additional signals across the common trace, such that only one of the first, second, or one of the additional signals couples with the common trace at any one time.
REFERENCES:
patent: 5140327 (1992-08-01), Bruce et al.
patent: 5323044 (1994-06-01), Rumennik et al.
patent: 6160276 (2000-12-01), Mohsen
Gedamu Elias
Man Denise
Hewlett--Packard Development Company, L.P.
Ngo Ngan V.
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