Multiplexing/demultiplexing unit arranged on a multi-surface int

Details Multiplexing/demultiplexing unit arranged on a multi-surface int Multiplexing/demultiplexing unit arranged on a multi-surface int

1996-10-01

1998-08-04

Nguyen, Chau

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370503, 370535, H04J 322

Patent

active

057905401

ABSTRACT:
The present invention relates to a multiplexing/demultiplexing unit constructed as an integrated circuit and as a block on a sub-surface of a silicon surface, such as a digital Bi-CMOS circuit and utilizing a CMOS section laid on said circuit, wherein a first sub-surface of a silicon surface carries a first array (41') of signal input and output circuits, and a second sub-surface carries a second array (41") of input and output circuits. A region (50) is located on the silicon surface between the first and the second sub-surfaces or located in some corresponding manner and is intended to carry control logic (51), memory stores (52), buffer circuits (53), synchronizing circuit arrangement (54) and the requisite conductors and functions to process signals, store signals and transmit the processed signals on selected output circuits both when multiplexing and demultiplexing signals.

REFERENCES:
patent: 4166212 (1979-08-01), Judeinstein
patent: 4300232 (1981-11-01), Kato
patent: 4656620 (1987-04-01), Cox
patent: 5130984 (1992-07-01), Cisneros
patent: 5198684 (1993-03-01), Sudo
patent: 5327422 (1994-07-01), Abefelt et al.
patent: 5365519 (1994-11-01), Kozaki et al.
patent: 5414698 (1995-05-01), Adams
patent: 5416773 (1995-05-01), Gamm

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